ArticlesBlog

Memory Chip Organization Part 1 – Georgia Tech – HPCA: Part 4

Memory Chip Organization Part 1 – Georgia Tech – HPCA: Part 4


So we have seen what a single
bit in memory looks like. Now let’s see how the whole
chip is organized. We said already that we have these
word lines that activate cells. We have a number of word lines, and the thing that decides which word line
gets activated is called a row decoder. What we give to the row decoder is
some bits of the address that tallied which of the word lines to activate. It can only activate one
word line at a time. So this is a real decoder. You give it a number. It activates a line that
corresponds to that number. In memory, we call this row address. There is also a bit line here, and
if you remember, a memory cell exists at every intersection between
this bit line and a word line. So what a word line does
is it connects this cell, this cell, this cell, or
this cell to the bit line. So by supplying, let’s say,
two bits of the address, which was which of the four bits would
be outputting on this one bit line. Of course,
there are more bit lines than just one. And this, for example,
is a 16 bit memory. It’s a four-by-four bit memory. Four bits can output to
the same bit line, and there are four bits activated
by each of the word lines, so when we select the row,
four bits get output out of here. Now bit lines are very long. And as we said, the cell is either
a relatively weak SRAM cell, so it will slowly pull the bit line one way
or the other, or it is a DRAM cell that discharges a relatively small capacitor
into this relatively long bit line. If we discharge a small
capacitor into a long bit line, the voltage on the bit line will change,
but it will change relatively little. It will not change all the way to
the level that corresponds to a one or to a zero. If we have a weak cell,
we don’t want to wait for that cell to raise the whole
bit line one way or the other. This is why the bit lines are connected
to a device called sense amplifier. What it does is it senses the small
changes on the bit line and amplifies them. So it’s really helping the cell raise or
lower the voltage on the bit line. And it has relatively
powerful circuitry for each bit line, so it’s significantly
bigger than a single row of cells, but you only need one of these
at the end of the bit line. You don’t need one of
these at every cell. So you have relatively small and
weak cells, and you have this beefy thing here that is helping
them raise or lower the bit line. The signals that are produced by
the sense amplifier, which are now correctly one or zero bits, go to
a storage element called row buffer. The row buffer stores
the correct values that we read from the whole row of cells. So in this case, the row buffer will
contain four bits because that’s how many bits are there in the row. The row buffer feeds the data it latched to another decoder that is
called a column decoder. This decoder selects the correct
bit among these four, let’s say, using the column address, which is another part of the data
address, and it outputs a single bit. If we want to build something that has
more than just one bit of data for each location, we will replicate this. So we will have, let’s say,
two of these, give them the same row and column address, and
now they output a two bit value.

Comments (5)

  1. Very effective explanation! thank you…

  2. but why ram 62256 is 9 rows address and 6 columns address so the data matrix would be 81×36=2916 bits while the datasheet says it's 512×512=262144 bits.can you explain?

  3. Thank you so much. Can you explain the working of 16 bit memory chip with 1T1D DRAM

  4. it is really a good sharing. thanks

  5. Thankyu so much sir

Comment here